Codenamed Sierra Forest and Granite Rapids, the next generation of Intel Xeon processors will feature new core designs and focus on memory and I/O.
Intel used the Hot Chips 2023 show to introduce the next generation of its Xeon processors, codenamed Sierra Forest and Granite Rapids. This will be the first generation of Xeon processors with different core designs: the new Efficient-core (E-core) architecture and existing Performance-core (P-core) architecture.
The new processors will be considerably beefier than the previous generation, codenamed Sapphire Rapids. They will feature up to 144 cores and emphasize greater memory and I/O bandwidth performance, two areas where Xeon has lagged behind AMD’s Epyc processors.
Intel claims the Sierra Forest processors with E-cores will offer up to 2.5 times better rack density and 2.4 times higher performance per watt than Sapphire Rapids, while the Granite Rapids processors with P-cores will provide 2 to 3 times the performance in mixed AI workloads, which it attributes in part to an improvement in memory bandwidth of up to 2.8 times.
P-core is high performance and meant for maximum processing, while E-core is a lower-level processing core for less compute-intensive tasks. Not every computer process requires a high-performance CPU, so using a P-core on something like file and print was overkill. Conversely, E-core uses less power.
Sierra Forest and Granite Rapids also incorporate a chiplet design rather than one monolithic piece of silicon. This will allow Intel to mix and match P-core and E-core designs for custom silicon.
Granite Rapids follows Sapphire Rapids as a traditional Xeon data center processor. Each P-core comes with 2MB of L2 cache and 4MB of L3. Intel did not disclose the core count for Granite Rapids, but it did say it will support up to eight sockets in a single server.
The architecture for the P-cores supports something Intel calls Advanced Matrix Extensions (AMX) for deep learning processing, with FP16 acceleration. FP16 is a standard extension for AI processing, and most AI processors target FP16.
Sierra Forest’s E-cores appear meant to compete with the Arm processors from Ampere, Fujitsu, and other makers of Arm-based server silicon. In this case, Intel did reveal the core count: up to 144 cores optimized for power efficiency. Sierra Forest is meant for single- and dual-socket systems and has a TDP of around 200W, which these days is low power.
The Sierra Forest processors also feature much beefier memory controllers, supporting 12 channels (a nice boost compared to eight channels in Sapphire Rapids) of DDR5-6400 memory and 136 lanes of PCIe 5.0 / CXL 2.0 interfacing. In addition to the DDR memory, the fifth-generation Xeon’s will support the new MCR memory Intel developed that provides 30% to 40% more memory bandwidth than standard DIMMs.
The fifth-generation Xeon chips are planned for release next year.
Hot Chips is an annual event that offers an extremely deep technical dive into all things electrical engineering. It’s held each August at Stanford University, which is the alma mater of many significant chip engineers, including Intel’s Pat Gelsinger and Nvidia’s Jensen Huang.
